MDDR I/F

Moble DDR SDRAM Memory I/F IP mDDRC 333A

General Description

Product Highlights

- Complete mobile DDR SDRAM solution including memory controller and physical interface module (PHY)
- Low read data capture latency achieved by a unique flop-based logic
- Patent-pending automatic self-adjusting technology eliminates system level timing issues
- Fast turn-around time between read and write operations
- Physical implementation challenges resolved through PHY macros
- All low power nodes supported
- Support for 1 to 8 chip-select signals and 4 or 8 banks on each chip select
- Parameterizable data bus width and ECC width
- 24 command deep pipeline hides access latency
- Support for built in read-modify-write command
- Fully configurable ODT window
- Software controlled initialization sequence

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