SRAM

"E³ (E-Cube) Series" SRAM Compiler

General Description

E³(Ecological, Efficient, Easy-to-Use) series SRAM compiler reduces standby leakage more than 80 percent comparing to the conventional ultra-low leakage SRAM computer, by utilizing uniquely developed self-back-bias technology (patent pending)
We call this statement as a hibernation mode (HBM), and it provides efficient solution to reduce the leakage for mobile applications to be used in standby mode. 　Moreover, SRAM can be implemented in the SOC without changing any usage, because of its simple structure of utilizing regular single power supply.

HBM Features

- Without loosing contents of memory, SRAM can reduce leakage at standby mode.
Differed from the power supply interception method, this technology will be able to return SRAM back into the previous state with the written data and even the output date at read mode. Special control at system side is not required.
- No area penalty.
In the feature of this technology, the leakage reduction is realized without increasing the area even with added low power mechanism.
- High-speed return from standby

Optimization of the whole SRAM circuit

To achieve low power consumption, circuit optimization is executed by various combinations of circuit design techniques.

- use of multi-Vth Tr, optimization of the Tr size
- optimization of the sense amplifier operation
- clock signal control

As well as leakage reduction, it offers area optimized, high performance and dynamic low power SRAM circuits.

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